1. Field of the Invention
This invention relates to a metal-oxide-semiconductor (MOS) transistor and in particular to a drifted-drain MOS transistor suitable for high voltage operation.
2. Description of the Prior Art
MOS transistors are devices consisting of diffused source and drain regions on either side of a P or N channel region, and a gate electrode insulated from the channel by silicon oxide. In some instances, the gate dielectric may be a sandwich such as SiO.sub.2 /Si.sub.3 N.sub.4. When the proper control voltage is applied to the gate, the "channel" is accumulated, allowing carriers to flow between the source and the drain. A conventional P channel MOS transistor is illustrated in FIG. 1, by way of example. The transistor is formed with an N type substrate, having two P regions adjacent to the source and drain with a gate electrode interposed between the source and drain. The body region is contacted with an N+ region.
Integrated circuits which operate at relatively high voltages generally require MOS transistors that are capable of withstanding the full operating voltage of the circuit. Conventional MOS structures of the P channel or N channel type generally are not capable of sustaining high voltage operation and are subject to breakdown when high voltages are applied. The breakdown voltage is limited by field plate induced breakdown or by planar junction breakdown. The field plate induced breakdown occurs when the maximum breakdown voltage is exceeded at a junction in the vicinity of a biased gate of the MOS transistor. This maximum breakdown voltage is determined by the distance between the gate electrode and the drain, and the dopant profile of the drain junction. The planar junction breakdown is determined. by the radius of curvature of the drain junction and the dopant concentration of the substrate. Breakdown occurs when the electric field in the vicinity of the junction exceeds the critical field of silicon.
One major objective of the semiconductor technology is to develop a transistor having a significant increase in the level of breakdown voltage. One type of transistor that can be adapted for this purpose is the drifted-drain MOS transistor, delineated in FIG. 2a. The drifted-drain MOS P- channel transistor is characterized by a lightly doped P- region that extends from the contacted drain region to the gate, thereby providing a conduction path from the region below the gate, which is inverted when the transistor is biased ON, to the P+ drain region. The P- region does not decrease the breakdown voltage of the device because the dopant concentration is kept sufficiently low. When a large reverse bias appears at the junction, this P- region depletes, thus increasing the breakdown voltage that is normally set by the radius of curvature of the P+ region. One characteristic of the drifted-drain MOS transistor is the bipolar current gain of the lateral PNP transistor which is formed when the drain region is biased as the emitter, the body region is biased as the base, and the source region is biased as the collector. With this type of configuration, the bipolar performance is limited by the ability of the lightly doped P- region to supply carriers, which is known as the emitter injection efficiency. This characteristic is largely determined by the relative concentrations of the "emitter" and the "base" regions. If the high voltage drifted-drain PMOS transistor of FIG. 2a is surrounded by a P- type region as shown in FIG. 2b, the current gain of the vertical PNP formed by using drain region 16 as the emitter, body region 28 as the base, and P- type region 30 as the collector may be higher than the lateral PNP formed by the drain (emitter), body (base), and source (collector) regions as described above. In certain circuit configurations, this vertical PNP action can be detrimental to its functioning.